Sequential state elements (SSEs) are used in digital circuits to store logical states from combinational logic circuitry and pass these logical states in a coordinated manner to other circuitry, such as other combinational logic circuits. One type of SSE is a master slave flip flop (MSFF). MSFF have been shown to operate highly reliably in accuracy and relatively robust with respect to noise. Unfortunately, the problem with MSFFs is that MSFFs are relatively slow and energy inefficient.
Accordingly, another type of SSE with greater energy efficiency and speed is the differential sense flip flop (DSFF). However, DSFF tend to suffer from floating nodes. These floating nodes tend to make the DSFF more subject to noise as floating nodes make the DSFF vulnerable to charge injection/ejection. As such most types of DSFF are sensitive to noise and are not very robust.
One type of DSFF is a strong arm flip flop (SAFF) which uses an equalizer transistor tries to deal with floating nodes. However, the SAFF tend to be unreliable. More specifically, the equalizer transistor makes the SAFF vulnerable to process variations where conductance mismatches cause the SAFF to prefer discharging one discharge node over the other leading to evaluation errors.
As such, an arrangement for an SSE is needed that provides greater speed but remains high reliable and robust to noise.